DP83843BVJE PHYTER
July 1999
DP83843BVJE PHYTER
General Description
Features
The DP83843BVJE is a full feature Physical Layer device — IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
with integrated PMD sublayers to support both 10BASE-T
and built-in filters
and 100BASE-X Ethernet protocols.
— IEEE 802.3u 100BASE-TX compatible - directly drives
standard Category 5 UTP, no need for external
This VLSI device is designed for easy implementation of
100BASE-TX transceiver
10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted
Pair media through an external transformer or to fiber — Fully Integrated and fully compliant ANSI X3.263 TP-
media via industry standard electrical/optical fiber PMD
PMD physical sublayer which includes adaptive equal-
transceivers. This device also interfaces directly to the
ization and BLW compensation
MAC layer through the IEEE 802.3u standard Media Inde-
— IEEE 802.3u 100BASE-FX compatible - connects direct-
pendent Interface (MII), ensuring interoperability between
ly to industry standard Electrical/Optical transceivers
products from different vendors.
— IEEE 802.3u Auto-Negotiation for automatic speed se-
The DP83843 is designed with National Semiconductor's
lection
advanced CMOS process. Its system architecture is based
on the integration of several of National's industry proven — IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface
core technologies:
— Integrated high performance 100 Mb/s clock recovery
— IEEE 802.3 ENDEC with AUI/10BASE-T transceiver
circuitry requiring no external filters
module to provide the 10 Mb/s functions
— Clock Recovery/Generator Modules from National's Fast — Full Duplex support for 10 and 100 Mb/s data rates
— MII Serial 10 Mb/s mode
Ethernet and FDDI products
— Fully configurable node/switch and 100Mb/s repeater
— FDDI Stream Cipher scrambler/descrambler for
modes
TP-PMD
— 100BASE-X physical coding sub-layer (PCS) and control — Programmable loopback modes for flexible system diag-
nostics
logic that integrates the core modules into a dual speed
Ethernet physical layer controller
— Flexible LED support
— ANSI X3T12 Compliant TP-PMD Transceiver
— Single register access to complete PHY status
technology with Baseline Wander (BLW) compensation
— MDIO interrupt support
— Individualized scrambler seed for 100BASE-TX applica-
tions using multiple PHYs
— Low power consumption for multi-port applications
— Small footprint 80-pin PQFP package
System Diagram
MII
10 AND/OR 100 Mb/s
ETHERNET MAC OR
100Mb/s REPEATER
CONTROLLER
MAGNETICS
10BASE-T or
100BASE-TX
DP83843
10/100 Mb/s
ETHERNET PHYSICAL LAYER
RJ-45
10BASE-T
or
100BASE-TX
25 MHz
CLOCK
STATUS
LEDS
100BASE-FX/
AUI
ThunderLAN
®
is a registered trademark of Texas Instruments.
TWISTER™ is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
©
1999 National Semiconductor Corporation
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
