Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
Parameter
TxCLK IN Transition Time (Figure 5 )
Min
Typ
Max Units
5
ns
ns
ns
ns
TCIP
TxCLK IN Period (Figure 6 )
TxCLK IN High Time (Figure 6 )
TxCLK IN Low Time (Figure 6)
14.7
0.35T
0.35T
T
55.6
TCIH
TCIL
0.5T 0.65T
0.5T 0.65T
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 4 )
LVDS High-to-Low Transition Time (Figure 4 )
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
Min
Typ
0.75
0.75
0
Max Units
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
LHLT
=
=
f
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
f
65 MHz
−0.30
1.90
4.10
6.30
8.50
0.20
2.40
4.60
6.80
9.00
2.20
4.40
6.60
8.80
10.70 11.00 11.20
12.90 13.20 13.40
f
40 MHz
−0.35
3.22
0
0.35
3.92
7.49
3.57
7.14
6.79
10.36 10.71 11.06
13.93 14.28 14.63
17.51 17.86 18.21
21.08 21.43 21.78
=
32.5
−0.40
4.00
0
0.40
4.80
9.20
MHz
4.40
8.80
8.40
12.80 13.20 13.60
17.20 17.60 18.00
21.60 22.00 22.40
26.00 26.40 26.80
2.5
THTC
TxIN Hold to TxCLK IN (Figure 6 )
0
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 7 ) TA=25˚C,VCC=3.3V
TxCLK IN to TxCLK OUT Delay (Figure 7 )
Transmitter Jitter Cycle-to-Cycle (Figures 12, 13 ) (Note 6)
3
3
5.5
7.0
=
=
f
TJCC
f
f
65 MHz
40 MHz
175
240
260
225
380
400
=
32.5
MHz
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
10
ms
ns
100
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This param-
eter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycle-
to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips
currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
3
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