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LM1881N 参数 Datasheet PDF下载

LM1881N图片预览
型号: LM1881N
PDF下载: 下载PDF文件 查看货源
内容描述: LM1881视频同步分离 [LM1881 Video Sync Separator]
分类和应用:
文件页数/大小: 12 页 / 302 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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LM1881, LM1881-X
Electrical Characteristics LM1881–X
V
CC
= 5V; R
SET
= 680 kΩ; T
A
= –40˚C to +85˚C by correlation with 100% electrical testing at T
A
=25˚C
Parameter
Supply Current
DC Input Voltage
Input Threshold Voltage
Input Discharge Current
Input Clamp Charge Current
R
SET
Pin Reference Voltage
Composite Sync. & Vertical
Outputs
Pin 2; V
IN
= 2V
Pin 2; V
IN
= 1V
Pin 6;
I
OUT
= 40 µA;
Logic 1
I
OUT
= 1.6 mA
Logic 1
Burst Gate & Odd/Even
Outputs
Composite Sync. Output
Vertical Sync. Output
Burst Gate Output
Odd/Even Output
Vertical Sync Width
Burst Gate Width
Vertical Default Time
2.7 kΩ from Pin 5 to V
CC
I
OUT
= 40 µA;
Logic 1
V
CC
= 5V
V
CC
= 12V
V
CC
= 5V
V
CC
= 12V
V
CC
= 5V
V
CC
= 12V
Outputs at
Logic 1
Pin 2
Conditions
V
CC
= 5V
V
CC
= 12V
1.3
55
6
0.2
1.10
4.0
11.0
2.4
10.0
4.0
11.0
Min
Typ
5.2
5.5
1.5
70
11
0.8
1.22
4.5
3.6
4.5
0.2
0.2
0.2
0.2
140
2.2
32
230
4
65
0.8
0.8
0.8
0.8
588
4.7
90
1.35
Max
10
12
1.8
85
16
Units
mA
V
mV
µA
mA
V
V
V
V
V
V
V
V
µs
µs
µs
I
OUT
= −1.6 mA; Logic 0; Pin 1
I
OUT
= −1.6 mA; Logic 0; Pin 3
I
OUT
= −1.6 mA; Logic 0; Pin 5
I
OUT
= −1.6 mA; Logic 0; Pin 7
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2:
For operation in ambient temperatures above 25˚C, the device must be derated based on a 150˚C maximum junction temperature and a package thermal
resistance of 110˚C/W, junction to ambient.
Note 3:
ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 kΩ resistor”.
Note 4:
Typicals are at T
J
= 25˚C and represent the most likely parametric norm.
Note 5:
Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Note 6:
Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the R
SET
pin (Pin 6).
Note 7:
Delay time between the start of vertical sync (at input) and the vertical output pulse.
Typical Performance Characteristics
R
SET
Value Selection
vs Vertical Serration
Pulse Separation
Vertical Default
Sync Delay Time
vs R
SET
00915007
00915008
3
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