Functional Description
(Continued)
Reading the Time Registers
Using the data-changed flag technique supports microproc-
essors with block move facilities as all the necessary time
data may be read sequentially and then tested for validity as
shown below
1) Read the control register address 0
This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers
2) Read time registers
All desired time registers are read
out in a block
3) Read the control register and test DCF
If DCF is cleared
(logic 0) then no clock setting pulses have after occurred
since step 1 All time data is guaranteed good and time
reading is complete
If DCF is set (logic 1) then a time change has occurred
since step 1 and time data may not be consistent Repeat
steps 2 and 3 until DCF is clear The control read of step 3
will have reset DCF automatically repeating the step 1 ac-
tion
Interrupt Programming
The interrupt timer generates interrupts at time intervals
which are programmed into the interrupt register A single
interrupt after delay or repeated interrupts may be pro-
grammed Table IIB lists the different time delays and the
data words that select them in the interrupt register
Once the interrupt register has been used to set up the
delay time and to select for single or repeat it takes no
further part in the workings of the interrupt system All activi-
ty by the processor then takes place in the control register
Initializing
1) Write 3 to the control register (AD0)
Clock timing contin-
ues interrupt register selected and interrupt timing stopped
2) Write interrupt control word to address 15
The interrupt
register is loaded with the correct word (chosen from Table
IIB) for the time delay required and for single or repeated
interrupts
3) Write 0 or 2 to the control register
Interrupt timing com-
mences Writing 0 selects the clock setting register onto the
data bus writing 2 leaves the interrupt register selected
Normal timekeeping remains unaffected
On Interrupt
Read the control register and test for Interrupt Flag (bit 0)
If the flag is cleared (logic 0) then the device is not the
source of the interrupt
If the flag is set (logic 1) then the clock did generate an
interrupt The flag is reset and the interrupt output is cleared
by the control register read that was used to test for inter-
rupt
Single Interrupt Mode
When appropriate write 0 or 2 to the control register to
restart the interrupt timer
Repeated Interrupt Mode
Timing continues synchronized with the control register
write which originally started interrupt timing No further in-
tervention is necessary from the processor to maintain tim-
ing
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt start stop set to 1) Timing
for the full delay period recommences when the interrupt
start stop bit is again loaded with 0 as normal
IMPORTANT NOTE
Using the interrupt timer places a con-
straint on the maximum Read Strobe width which may be
applied to the clock Normally all registers may be read from
with a t
RW
down to DC (i e CS and RD held continuously
low) When the interrupt timer is active however the maxi-
mum read strobe width that can be applied to the control
register (Addr 0) is 30 ms
This restriction is to allow the interrupt timer to properly re-
set when it times out Note that it only affects reading of the
control register all other addresses in the clock may be
accessed with DC read strobes regardless of the state of
the interrupt timer Writes to any address are unaffected
NOTES ON AC TIMING REQUIREMENTS
Although the Switching Time Waveforms show Microbus
control signals used for clock access this does not pre-
clude the use of the MM58274C in other non-Microbus sys-
tems
Figure 5
is a simplified logic diagram showing how the
control signals are gated internally to control access to the
clock registers From this diagram it is clear that CS could
be used to generate the internal data transfer strobes with
RD and WR inputs set up first This situation is illustrated in
Figure 6
The internal data busses of the MM58274C are fully CMOS
contributing to the flexibility of the control inputs When de-
termining the suitability of any given control signal pattern
for the MM58274C the timing specifications in AC Switching
Characteristics should be examined As long as these tim-
ings are met (or exceeded) the MM58274C will function cor-
rectly
When the MM58274C is connected to the system via a pe-
ripheral port the freedom from timing constraints allows for
very simple control signal generation as in
Figure 7
For
reading (Figure
7a
) Address CS and RD may be activated
simultaneously and the data will be available at the port
after t
AD
-max (650 ns) For writing (Figure
7b
) the address
and data may be applied simultaneously 70 ns later CS and
WR may be strobed together
10
NSC [ NATIONAL SEMICONDUCTOR ]
