NTE6850 参数 Datasheet PDF下载

NTE6850

Integrated Circuit

NMOS, Asynchronous Communications

Interface Adapter

Description:

The NTE6850 Asynchronous Communications Interface Adapter provides the data formatting and

control to interface serial asynchronous data communications information to bus organized systems

such as the NTE6800 Microprocessing Unit.

The bus interface of the NTE6850 includes select, enable, read/write, interrupt and bus interface logic

to allow data transfer over an 8–bit bidirectional data bus. The parallel data of the bus system is serial-

ly transmitted and received by the asynchronous data interface, with proper formatting and error

checking. The functional configuration of the ACIA is programmed via the data bus during system

initialization. A programmable control register provides variable word lengths, clock division ratios,

transmit control, receive control, and interrupt control. For peripheral or modem operation, three con-

trol lines are provided. These lines allow the ACIA to interface directly with the NTE6860 0–600 bps

digital modem.

Features:

D

8–Bit and 9–Bit Transmission

D

Optional Even and Odd Parity

D

Parity, Overrun and Framing Error Checking

D

Programmable Control Register

D

Optional

÷1, ÷16,

and

÷64

Clock Modes

D

Up to 1.0 Mbps Transmission

D

False Start Bit Deletion

D

Peripheral/Modem Control Functions

D

Double Buffered

D

One–Stop or Two–Stop Bit Operation

Absolute Maximum Ratings:

Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V

Input Voltage, V

in

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V

Operating Temperature Range, T

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C

Storage Temperature Range, T

stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C

Thermal Resistance, Junction–to–Ambient, R

thJA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages

or electric fields; however, it is advised that normal precautions be taken to avoid application

of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability

of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.

either V

SS

or V

CC

).