NTE937M
Integrated Circuit
JFET Input Operational Amplifier
Description:
The NTE937M is a monolithic JFET input operational amplifier in an 8–Lead DIP type package incor-
porating well–matched, high voltage JFET’s on the same chip with standard bi–polar transistors. This
amplifier features low input bias and offset currents, low offset voltage and offset voltage drift, coupled
with offset adjust which does not degrade drift or common–mode rejection. It is also designed for high
slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f
noise corner.
Advantages:
D
Replaces Expensive Hybrid and Module FET OP Amps
D
Rugged JFET’s Allow Blow–Out Free Handling Compared with MOSFET Input Device
D
Excellent for Low Noise Applications using either High or Low Source Impedance – Very Low
1/f Corner
D
Offset Adjust does not Degrade Drift or Common–Mode Rejection as in Most Monolithic Amplifiers
D
New Output Stage Allows use of Large Capacitive Loads (10,000pF) without Stability Problems
D
Internal Compensation and Large Differential Input Voltage Capability
Applications:
D
Precision High Speed Integrators
D
Fast D/A and A/D Converters
D
High Impedance Buffers
D
Wideband, Low Noise, Low Drift Amplifiers
D
Logarithmic Amplifiers
D
Photocell Amplifiers
D
Sample and Hold Circuits
Absolute Maximum Ratings:
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18V
Maximum Power Dissipation (at +25°C, Note 1), P
d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±30V
Input Voltage Range (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±16V
Output Short–Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Maximum Operating Junction Temperature (Note 1), T
J
max . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Lead Temperature (During Soldering, 10sec), T
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Thermal Resistance, Junction–to–Ambient (Note 1), R
thJC
. . . . . . . . . . . . . . . . . . . . . . . . . +155°C/W
Note 1. The maximum power dissipation for this device must be derated at elevated temperatures
and is dictated by T
J
max, R
thJC
, and the ambient temperature, T
A
. The maximum available
power dissipation at any temperature is P
d
= (T
J
max – T
A
)/R
thJC
or the +25°C P
d
max, which-
ever is less.
Note 2. Unless otherwise specified, the absolute maximum negative input voltage is equal to the
negative power supply voltage.
NTE [ NTE ELECTRONICS ]
