Numonyx™ Embedded Flash Memory (J3 v. D)
2.1
Figure 1:
Block Diagram
Memory Block Diagram (32, 64 and 128 Mbit)
DQ
0
- DQ
15
V
CCQ
Output
Buffer
Input Buffer
Output
Latch/Multi pl exer
Query
Write Buffer
Data
Registe r
Identifier
Register
Status
Register
I/O Logic
CE
Logic
V
CC
BYTE#
CE
0
CE
1
CE
2
WE#
OE#
RP#
Command
User
Interface
A
0
- A
2
Data
Comparator
Multiplexer
32-Mbit: A
0
- A
21
64-Mbit: A
0
- A
22
128-Mbit: A
0
- A
23
Input Buffer
Y-Decoder
Y-Gating
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty -eight
Write State
Machine
Program/Erase
Voltage Switch
STS
V
PEN
V
CC
GND
Address
Latch
Address
Counter
X-Decoder
128-Kbyte Blocks
Figure 2:
Numonyx™ Embedded Flash Memory (J3 v. D) Memory Block Diagram (256
Mbit)
Vcc
28F128J3
CE1
CE#
Upper Address
CE0
Device
D[15-0]
A[23-A0]
A[23-A0]
CE2
A24
D[15-0]
28F128J3
CE1
Lower Address
CE0
Device
D[15-0]
A[23-A0]
CE2
Datasheet
10
November 2007
308551-05
NUMONYX [ NUMONYX B.V ]
