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M25P16-VMN3TG 参数 Datasheet PDF下载

M25P16-VMN3TG图片预览
型号: M25P16-VMN3TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位串行闪存, 75 MHz的SPI总线接口 [16 Mbit, serial Flash memory, 75 MHz SPI bus interface]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 55 页 / 1057 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P16
Instructions
6.12
Release from Deep Power-down and Read Electronic
Signature (RES)
To take the device out of Deep Power-down mode, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The instruction can also be used to read, on Serial Data output (Q), the old-style 8-bit
electronic signature, whose value for the M25P16 is 14h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit electronic
signature that is read by the Read Identifier (RDID) instruction. The old-style electronic
signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit electronic
signature, and the Read Identifier (RDID) instruction.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the old-style 8-bit electronic signature of the device, and can be applied even if the
Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge
of Serial Clock (C). Then, the old-style 8-bit electronic signature, stored in the memory, is
shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the electronic signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the electronic signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by t
RES2
, and Chip Select (S)
must remain High for at least t
RES2
(max). Once in the Standby Power mode, the device
waits to be selected, so that it can receive, decode and execute instructions.
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