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M25P20 参数 Datasheet PDF下载

M25P20图片预览
型号: M25P20
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位,低电压,串行闪存与50MHz的SPI总线接口 [2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 50 页 / 964 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P20  
Revision history  
Table 24. Document revision history (continued)  
Date  
Revision  
Changes  
50MHz operation added (see Table 20: AC Characteristics (50MHz  
Operation, Device Grade 6)). All packages are ECOPACK®. Blank option  
removed from under Plating Technology in Table 23: Ordering Information  
Scheme. MLP package renamed as VFQFPN, silhouette and package  
mechanical drawing updated (see package silhouette on page 1 and  
Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat  
Package No lead, 6x5mm, Package Outline. Note added to <Blue>Figure  
26. and Figure 27 Read Identification (RDID) instruction added.  
01-Dec-2005  
7.0  
tRES1 and tRES2 modified in Table 20: AC Characteristics (50MHz  
Operation, Device Grade 6). Titles of Figure 27 and Table 22 corrected.  
22-Dec-2005  
8.0  
The data contained in Table 11, Table 16 and Table 18 is no longer  
preliminary data.  
Figure 3: Bus Master and memory devices on the SPI Bus modified and  
Note 2 added.  
40MHz frequency condition modified for ICC3 in Table 14: DC  
Characteristics (Device Grade 3).  
Table 16: Instruction Times (Device Grade 3) shows preliminary data.  
14-Apr-2006  
9
Device Grade distinction removed, Condition changed for the Data  
Retention parameter in Table 11: Data Retention and Endurance.  
VWI parameter for Device Grade 3 added to Table 8: Power-Up Timing  
and VWI Threshold.  
SO8 package specifications updated (see Figure 26 and Table 21).  
/X Process added to Table 23: Ordering Information Scheme.  
tRES1 and tRES2 parameter timings changed for devices produced with the  
“X” process technology in Table 18 and Table 19.  
05-Jun-2006  
10-Dec-2007  
10  
11  
SO8 Narrow package specifications updated (see Figure 26 and  
Table 21).  
Applied Numonyx branding.  
49/50