M25P20
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3.
Bus Master and memory devices on the SPI Bus
V
SS
V
CC
R
(2)
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
V
CC
V
SS
R
(2)
SPI Memory
Device
R
(2)
C Q D
V
CC
V
SS
SPI Memory
R
(2)
Device
SPI Memory
Device
C Q D
V
CC
V
SS
SPI Bus Master
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the t
SHCH
requirement is met).
9/50
NUMONYX [ NUMONYX B.V ]
