Initial delivery state
Figure 28. Power-up timing
VCC
VCC(max)
Program, erase and write commands are rejected by the device
Chip selection not allowed
VCC(min)
Reset state
of the
device
VWI
tPUW
tVSL
Read access allowed
M25PX64
Device fully
accessible
time
AI04009C
Table 11.
Symbol
t
VSL(1)
t
PUW(1)
V
WI(1)
Power-up timing and V
WI
threshold
Parameter
V
CC
(min) to S Low
Time delay to write instruction
Write inhibit voltage
Min
30
1
1.5
10
2.5
Max
Unit
µs
ms
V
1. These parameters are characterized only.
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
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