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M25PX64 参数 Datasheet PDF下载

M25PX64图片预览
型号: M25PX64
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 66 页 / 1330 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PX64
Table 17.
AC characteristics
(1)
(continued)
DC and AC parameters
Test conditions specified in
Table 13
and
Table 14
Symbol
t
W
Alt.
Parameter
Write status register cycle time
Page program cycle time (256 bytes)
t
PP(8)
Page program cycle time (n bytes)
Program OTP cycle time (64 bytes)
t
SSE
t
SE
t
BE
1. Preliminary data.
2. Typical values given for T
A
= 25° C.
3. t
CH
+ t
CL
must be greater than or equal to 1/ f
C
.
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
7. V
PPH
should be kept at a valid level until the program or erase operation has completed and its result
(success or failure) is known.
8. When using the page program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes (1
n
256).
9. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Min
Typ
(2)
1.3
0.8
int(n/8) × 0.025
(9)
0.2
70
0.7
68
Max
15
Unit
ms
ms
5
ms
150
3
160
ms
s
s
Subsector erase cycle time
Sector erase cycle time
Bulk erase cycle time
Bulk erase cycle time (V
PP
= V
PPH
)
35
Figure 30. Serial input timing
tSHSL
S
tCHSL
C
tDVCH
tCHDX
DQ0
MSB IN
tCLCH
LSB IN
tCHCL
tSLCH
tCHSH
tSHCH
DQ1
High Impedance
AI13728
59/66