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M28W320FCT70N6E 参数 Datasheet PDF下载

M28W320FCT70N6E图片预览
型号: M28W320FCT70N6E
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位(2MB X16 ,引导块) 3V供应闪存 [32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 69 页 / 1276 K
品牌: NUMONYX [ NUMONYX B.V ]
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Bus operations  
M28W320FCT, M28W320FCB  
3
Bus operations  
There are six standard bus operations that control the device. These are Bus Read, Bus  
Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus  
Operations, for a summary.  
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the  
memory and do not affect bus operations.  
3.1  
Read  
Read Bus operations are used to output the contents of the Memory Array, the Electronic  
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and  
Output Enable must be at V in order to perform a read operation. The Chip Enable input  
IL  
should be used to enable the device. Output Enable should be used to gate data onto the  
output. The data read depends on the previous command written to the memory (see  
Command Interface section). See Figure 8: Read AC Waveforms, and Table 16: Read AC  
Characteristics, for details of when the output becomes valid.  
Read mode is the default state of the device when exiting Reset or after power-up.  
3.2  
Write  
Bus Write operations write Commands to the memory or latch Input Data to be  
programmed. A write operation is initiated when Chip Enable and Write Enable are at V  
IL  
with Output Enable at V . Commands, Input Data and Addresses are latched on the rising  
IH  
edge of Write Enable or Chip Enable, whichever occurs first.  
See Figure 9 and Figure 10, Write AC Waveforms, and Table 17 and Table 18, Write AC  
Characteristics, for details of the timing requirements.  
3.3  
3.4  
Output Disable  
The data outputs are high impedance when the Output Enable is at V .  
IH  
Standby  
Standby disables most of the internal circuitry allowing a substantial reduction of the current  
consumption. The memory is in stand-by when Chip Enable is at V and the device is in  
IH  
read mode. The power consumption is reduced to the stand-by level and the outputs are set  
to high impedance, independently from the Output Enable or Write Enable inputs. If Chip  
Enable switches to V during a program or erase operation, the device enters Standby  
IH  
mode when finished.  
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