M29W160ET, M29W160EB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the Program/
Erase Controller.
Read and Bus Write operations after t
RHEL
Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
or
PHEL
t
, whichever occurs last. See the Ready/Busy
Holding RP at V will temporarily unprotect the
ID
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V . Ready/Busy is high-im-
OL
pedance during Read mode, Auto Select mode
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
is High, V . When BYTE is Low, V , these pins
IH
IL
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V , this pin behaves as a
IH
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V , this pin behaves as an address
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
IL
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
lect is Low, V , the memory is in 8-bit mode, when
IL
it is High, V , the memory is in 16-bit mode.
IH
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for all operations (Read, Pro-
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
gram, Erase etc.).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
CC
High, V , all other pins are ignored.
IH
V
. This prevents Bus Write operations from ac-
LKO
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
SS
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
.
CC3
A Hardware Reset is achieved by holding Reset/
V
Ground. The V Ground is the reference for
SS
SS
Block Temporary Unprotect Low, V , for at least
IL
all voltage measurements. The two V pins of the
SS
t
. After Reset/Block Temporary Unprotect
goes High, V , the memory will be ready for Bus
PLPX
device must be connected to the system ground.
IH
10/40
NUMONYX [ NUMONYX B.V ]
