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M29W160ET90N6 参数 Datasheet PDF下载

M29W160ET90N6图片预览
型号: M29W160ET90N6
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位(2MB ×8或1Mb的X16 ,引导块) 3V供应闪存 [16 Mbit (2Mb x8 or 1Mb x16, Boot Block) 3V Supply Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 40 页 / 1035 K
品牌: NUMONYX [ NUMONYX B.V ]
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M29W160ET, M29W160EB  
SUMMARY DESCRIPTION  
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)  
non-volatile memory that can be read, erased and  
reprogrammed. These operations can be per-  
formed using a single low voltage (2.7 to 3.6V)  
supply. On power-up the memory defaults to its  
Read mode where it can be read in the same way  
as a ROM or EPROM.  
The memory is divided into blocks that can be  
erased independently so it is possible to preserve  
valid data while old data is erased. Each block can  
be protected independently to prevent accidental  
Program or Erase commands from modifying the  
memory. Program and Erase commands are writ-  
ten to the Command Interface of the memory. An  
on-chip Program/Erase Controller simplifies the  
process of programming or erasing the memory by  
taking care of all of the special operations that are  
required to update the memory contents.  
command set required to control the memory is  
consistent with JEDEC standards.  
The blocks in the memory are asymmetrically ar-  
ranged, see Figures 5 and 6, Block Addresses.  
The first or last 64 KBytes have been divided into  
four additional blocks. The 16 KByte Boot Block  
can be used for small initialization code to start the  
microprocessor, the two 8 KByte Parameter  
Blocks can be used for parameter storage and the  
remaining 32K is a small Main Block where the ap-  
plication may be stored.  
Chip Enable, Output Enable and Write Enable sig-  
nals control the bus operation of the memory.  
They allow simple connection to most micropro-  
cessors, often without additional logic.  
The memory is offered TSOP48 (12 x 20mm) and  
TFBGA48 (0.8mm pitch) packages. The memory  
is supplied with all the bits erased (set to ’1’).  
The end of a program or erase operation can be  
detected and any error conditions identified. The  
Figure 2. Logic Diagram  
Table 1. Signal Names  
A0-A19  
DQ0-DQ7  
DQ8-DQ14  
DQ15A–1  
E
Address Inputs  
Data Inputs/Outputs  
Data Inputs/Outputs  
Data Input/Output or Address Input  
Chip Enable  
V
CC  
20  
15  
A0-A19  
DQ0-DQ14  
DQ15A–1  
W
E
G
Output Enable  
M29W160ET  
M29W160EB  
W
Write Enable  
G
RB  
RP  
Reset/Block Temporary Unprotect  
Ready/Busy Output  
Byte/Word Organization Select  
Supply Voltage  
RP  
RB  
BYTE  
BYTE  
V
CC  
V
SS  
V
Ground  
SS  
AI06849B  
NC  
Not Connected Internally  
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