M29W160ET, M29W160EB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V
0.2V. For the Standby current
level see Table 11, DC Characteristics.
CC
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC3
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
til the operation completes.
Automatic Standby. If CMOS levels (V
0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
Inputs, applying a Low signal, V , to Chip Enable
IL
and Output Enable and keeping Write Enable
duced to the Standby Supply Current, I
. The
CC2
High, V . The Data Inputs/Outputs will output the
IH
Data Inputs/Outputs will still output data if a Bus
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
ally used in applications. They require V to be
ID
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
able must remain High, V , during the whole Bus
IH
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
Table 2. Bus Operations, BYTE = V
IL
Data Inputs/Outputs
Address Inputs
Operation
E
G
W
DQ15A–1, A0-A19
DQ14-DQ8
DQ7-DQ0
Data Output
Data Input
Hi-Z
V
V
V
IH
Bus Read
Cell Address
Hi-Z
IL
IL
IL
IH
IH
V
V
V
V
V
Bus Write
Command Address
Hi-Z
IL
Output Disable
Standby
X
X
Hi-Z
IH
V
X
X
X
Hi-Z
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
V
Hi-Z
Hi-Z
20h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
C4h (M29W160ET)
49h (M29W160EB)
IH
IL
ID
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
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NUMONYX [ NUMONYX B.V ]
