M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 6.
Write Enable controlled Program waveforms (8-bit mode)
3rd cycle
tAVAV
A0-A20/
A–1
555h
tAVWL
tELWL
E
tGHWL
G
tWLWH
W
tDVWH
DQ0-DQ7/
DQ8-DQ15
AOh
PD
tWHDX
tWHWH1
DQ7 DOUT
tGHQZ
DOUT
tWHWL
tWHEH
PA
tWLAX
tELQV
PA
4th cycle
Data Polling
tAVAV
Read cycle
Command Interface
tGLQV
tAXQX
AI12779
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status register Data Polling bit and by a read operation that outputs the data, D
OUT
, programmed by the previous
Program command.
2. PA is address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see
4.
5.
Addresses differ in x8 mode.
See
and
for details on the timings.
37/90
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