Signal descriptions
M29W800DT, M29W800DB
2
Signal descriptions
See
and
for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A18)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the internal state machine.
2.2
Data inputs/outputs (DQ0-DQ7)
The data inputs/outputs output the data stored at the selected address during a bus read
operation. During bus write operations they represent the commands sent to the command
interface of the internal state machine.
2.3
Data inputs/outputs (DQ8-DQ14)
The data inputs/outputs output the data stored at the selected address during a bus read
operation when BYTE is High, V
IH
. When BYTE is Low, V
IL
, these pins are not used and are
high impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
2.4
Data input/output or address input (DQ15A-1)
When BYTE is High, V
IH
, this pin behaves as a data input/output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text
consider references to the data input/output to include this pin when BYTE is High and
references to the address inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip enable (E)
The chip enable, E, activates the memory, allowing bus read and bus write operations to be
performed. When Chip Enable is High, V
IH
, all other pins are ignored.
2.6
Output enable (G)
The output enable, G, controls the bus read operation of the memory.
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