M39P0R9080E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory
256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
Feature summary
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Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash memory
– 1 die of 256 Mbit (4 Banks of 4Mb x16)
Low
Power Synchronous Dynamic RAM
Supply voltage
– V
DDF
= V
CCP
= V
DDQ
= 1.7 to 1.95V
– V
PPF
= 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
ECOPACK® package available
FBGA
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TFBGA105 (ZAD)
9 x 11mm
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100,000 program/erase cycles per block
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
– WP
F
for Block Lock-Down
– Absolute Write Protection with V
PPF
= V
SS
Common Flash Interface (CFI)
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Flash memory
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Synchronous / asynchronous read
– Synchronous Burst Read mode:
108MHz, 66MHz
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LPSDRAM
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– Asynchronous Page Read mode
– Random Access: 96ns
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Programming time
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple Bank Memory Array: 64 Mbit
Banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
Security
– 64-bit unique device number
– 2112-bit user programmable OTP Cells
256 Mbit synchronous dynamic RAM
– Organized as 4 Banks of 4 MWords, each
16 bits wide
Synchronous burst read and write
– Fixed Burst Lengths: 1, 2, 4, 8 words or Full
Page
– Burst Types: Sequential and Interleaved.
– Clock Frequency: 133 MHz (7.5ns speed
class)
– Clock Valid to Output Delay (CAS Latency):
3 at 133 MHz
Automatic and controlled precharge
Low-power features:
– Partial Array Self Refresh (PASR),
– Automatic Temperature Compensated Self
Refresh (TCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
Auto Refresh and Self Refresh
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November 2007
Rev 2
1/23
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