DC and AC parameters
Table 25.
Symbol
t
AVAV
t
AVEH
t
AVLH
t
DVEH
t
EHAX
Chip Enable Controlled Timings
t
EHDX
t
EHEL
t
EHGL
t
EHWH
t
ELKV
t
ELEH
t
ELLH
t
ELQV
t
GHEL
t
LHAX
t
LLLH
t
WHEL(2)
t
WLEL
Protection Timings
t
EHVPL
t
QVVPL
t
VPHEH
t
VPS
t
CS
t
CP
t
CH
t
DS
t
AH
t
DH
t
CPH
M58LT128HST, M58LT128HSB
Write AC characteristics, Chip Enable controlled
(1)
M58LT128HST/B
Alt
t
WC
Parameter
85
Address Valid to Next Address Valid
Address Valid to Chip Enable High
Address Valid to Latch Enable High
Data Valid to Chip Enable High
Chip Enable High to Address Transition
Chip Enable High to Input Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Clock Valid
Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Output Valid
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
Write Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable High to V
PP
Low
Output (Status Register) Valid to V
PP
Low
V
PP
High to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
50
10
50
0
0
25
0
0
9
50
10
85
17
9
10
25
0
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Min
200
ns
1. Sampled only, not 100% tested.
2. t
WHEL
has this value when reading in the targeted bank or when reading following a Set Configuration
Register command. System designers should take this into account and may insert a software No-Op
instruction to delay the first read in the same bank after issuing any command and to delay the first read to
any address after issuing a Set Configuration Register command. If the first read after the command is a
Read Array operation in a different bank and no changes to the Configuration Register have been issued,
t
WHEL
is 0 ns.
68/110
NUMONYX [ NUMONYX B.V ]
