N25Q128 - 1.8 V
XIP Operations
Figure 104. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)
S
C
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12
14 15 16 17 18 19 20 21 22 23
13
0
IO switches from Input to Output
Instruction
4
0
4
0
Xb
4
5
0
4
0
DQ0
DQ1
DQ2
4
4
Don’t Care
Don’t Care
5
6
1
2
5
6
1
2
1
2
5
6
1
2
5
6
1
2
5
6
6
DQ3
7
3
7
3
7
3
7
3
7
3
7
‘1’
A7-0
Dummy (ex.: 6)
Byte 2
Byte 1
A15-8
A23-16
XIP_VCR
Note:
Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP
mode and return to standard read mode.
10.3
XIP mode hold and exit
The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation
bit to be sent to the memory on DQ0 during the first dummy clock cycle.
The device decodes the XIP Confirmation bit with the scheme:
XIP Confirmation bit=0 means to hold XIP Mode
XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that
means codifying the first byte after the next chip select as an instruction code.
In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the
addresses is always Don't Care.
In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle
after the addresses are always Don't Care.
In Dual and Single I/O XIP mode, in presence of the RESET pin enabled (in devices with a
dedicated part number), a low pulse on that pin resets the XIP protocol as defined by the
Volatile Configuration Register, reporting the memory at the state of last power up, as
defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to
reset the memory (for devices with a dedicated part number) only when the device is
deselected. See Section 16: Ordering information.
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NUMONYX [ NUMONYX B.V ]
