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RC28F128P30B85 参数 Datasheet PDF下载

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型号: RC28F128P30B85
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆的StrataFlash嵌入式存储器 [Numonyx StrataFlash Embedded Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 99 页 / 1401 K
品牌: NUMONYX [ NUMONYX B.V ]
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P30  
14.0  
Special Read States  
The following sections describe non-array read states. Non-array reads can be  
performed in asynchronous read or synchronous burst mode. A non-array read  
operation occurs as asynchronous single-word mode. When non-array reads are performed in  
asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-  
array read operation occurs as synchronous burst mode, the same word of data  
requested will be output on successive clock edges until the burst length requirements  
are satisfied.  
Refer to the following waveforms for more detailed information:  
Figure 14, “Asynchronous Single-Word Read (ADV# Low)” on page 33  
Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on page 33  
Figure 17, “Synchronous Single-Word Array or Non-array Read Timing” on page 34  
14.1  
Read Status Register  
To read the Status Register, issue the Read Status Register command at any address.  
Status Register information is available to which the Read Status Register, Word  
Program, or Block Erase command was issued. Status Register data is automatically  
made available following a Word Program, Block Erase, or Block Lock command  
sequence. Reads from the device after any of these command sequences outputs the  
device’s status until another valid command is written (e.g. Read Array command).  
The Status Register is read using single asynchronous-mode or synchronous burst  
mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on  
DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs  
first) updates and latches the Status Register contents. However, reading the Status  
Register in synchronous burst mode, CE# or ADV# must be toggled to update status  
data.  
The Device Write Status bit (SR[7]) provides overall status of the device. Status  
register bits SR[6:1] present status and error information about the program, erase,  
suspend, VPP, and block-locked operations.  
Table 32: Status Register Description (Sheet 1 of 2)  
Status Register (SR)  
Default Value = 0x80  
Program  
Suspend  
Status  
Device Write EraseSuspend  
Program  
Status  
Block-Locked  
BEFP  
Status  
Erase Status  
VPP Status  
Status  
Status  
Status  
DWS  
7
ESS  
6
ES  
5
PS  
4
VPPS  
3
PSS  
2
BLS  
1
BWS  
0
Bit  
Name  
Description  
0 = Device is busy; program or erase cycle in progress; SR[0] valid.  
1 = Device is ready; SR[6:1] are valid.  
7
6
5
4
Device Write Status (DWS)  
Erase Suspend Status (ESS)  
Erase Status (ES)  
0 = Erase suspend not in effect.  
1 = Erase suspend in effect.  
0 = Erase successful.  
1 = Erase fail or program sequence error when set with SR[4,7].  
0 = Program successful.  
Program Status (PS)  
1 = Program fail or program sequence error when set with SR[5,7]  
November 2007  
Order Number: 306666-11  
Datasheet  
69