P30
Appendix F Ordering Information for SCSP Products
Figure 47: Decoder for SCSP P30
Flash Family 1/2
Flash #1
Flash #2
Flash #3
R D 4 8 F 4 0 0 0 P 0 Z B Q 0
RD = Intel
®
SCSP, leaded
P F = Intel
®
SCSP, lead-free
RC = 64-Ball Easy BG A, leaded
P C = 64-Ball Easy BG A, lead-free
T E = 56-Lead TSO P , leaded
JS = 56-Lead T SO P, lead-free
Package Designator
Flash #4
Flash Family 3/4
Device Details
0 = O riginal version of the product
(refer to the latest version of the
datasheet for details)
Ballout Designator
Q = Q UAD+ ballout
0 = Discrete ballout
Group Designator
48F = Flash Memory only
Flash Density
0
2
3
4
=
=
=
=
No die
64-Mbit
128-M bit
256-M bit
Param eter, M ux Configuration
B = Bottom Param eter, Non Mux
T = Top Param eter, Non M ux
I/O Voltage, CE# Configuration
Z = Individual Chip Enable(s)
V = Virtual Chip E nable(s)
V
C C
= 1.7 V – 2.0 V
V
C C Q
= 1.7 V – 3.6 V
Product Fam ily
P = Intel StrataF lash® Em bedded M em ory
0 = No die
Note:
For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations.
Table 50: Valid Combinations for Dual- Die Products
64-Mbit
RD48F2000P0ZBQ0
RD48F2000P0ZTQ0
PF48F2000P0ZBQ0
PF48F2000P0ZTQ0
128-Mbit
RD48F3000P0ZBQ0
RD48F3000P0ZTQ0
PF48F3000P0ZBQ0
PF48F3000P0ZTQ0
256-Mbit
RD48F4000P0ZBQ0
RD48F4000P0ZTQ0
PF48F4000P0ZBQ0
PF48F4000P0ZTQ0
512-Mbit
*
RD48F4400P0VBQ0
PF48F4400P0VBQ0
RC48F4400P0VB00
PC48F4400P0VB00
TE48F4400P0VB00
JS48F4400P0VB00
Note:
* The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density.
November 2007
Order Number: 306666-11
Datasheet
99
NUMONYX [ NUMONYX B.V ]
