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FEDS82V48540-01 参数 Datasheet PDF下载

FEDS82V48540-01图片预览
型号: FEDS82V48540-01
PDF下载: 下载PDF文件 查看货源
内容描述: 393,216字】 32位】 4银行FIFO , SGRAM [393,216-Word 】 32-Bit 】 4-Bank FIFO-SGRAM]
分类和应用: 先进先出芯片
文件页数/大小: 44 页 / 1411 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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OKI Semiconductor
MS82V48540
393,216-Word
×
32-Bit
×
4-Bank FIFO-SGRAM
FEDS82V48540-01
Issue Date:Nov. 8, 2002
GENERAL DESCRIPTION
The MS82V48540 is a 48-Mbit system clock synchronous dynamic random access memory. In addition to the
conventional random read/write access function, the MS82V48540 provides the automatic row address increment
function and automatic bank switching function. Therefore, if once the row and column addresses are set,
continuous serial accesses are possible while banks are automatically switched till input of the Precharge
command. The MS82V48540 is ideal for digital camera and TV buffer memory applications.
FEATURES
393,216 words
×
32 bits
×
4 banks memory (1,536 rows
×
256 columns
×
32 bits
×
4 banks)
Single 3.3 V
±0.3
V power supply
LVTTL compatible inputs and outputs
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (2, 3)
Automatic row address increment function and automatic bank switching function
Power Down operation and Clock Suspend operation
3,072 refresh cycles/64 ms
Auto refresh and self refresh capability
Package:
86-pin 400 mil plastic TSOP (II) (TSOPII86-P-400-0.50-K) (Product : MS82V48540-xTA)
x indicates speed rank.
PRODUCT FAMILY
Family
MS82V48540-7
MS82V48540-8
Max. Operating Frequency
143 MHz
125 MHz
Access Time
5 ns
6 ns
Package
86-pin Plastic TSOP (II) (400 mil)
1/44