¡ Semiconductor
MSM80C85AHRS/GS/JS
Table 3 MSM80C85AH Machine State Chart
Machine State
T
1
T
2
T
WAIT
T
3
T
4
T
5
T
6
T
RESET
T
HALT
T
HOLD
0
1
TS
¥
Status & Buses
S
1
, S
0
¥
¥
¥
¥
1
1
1
¥
0
¥
IO/M
¥
¥
¥
¥
0
(2)
0
(2)
Control
AD
0
– AD
7
¥
¥
¥
¥
TS
TS
TS
TS
TS
TS
RD, WR
1
¥
¥
¥
1
1
1
TS
TS
TS
INTA
1
¥
¥
¥
1
1
1
1
1
1
ALE
1
(1)
0
0
0
0
0
0
0
0
0
A
8
– A
15
¥
¥
¥
¥
¥
¥
¥
TS
TS
TS
0
(2)
TS
TS
TS
= Logic "0"
= Logic "1"
= High Impedance
= Unspecified
Notes:
(1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
(2) IO/M = 1 during T
4
- T
6
of INA machine cycle.
M
1
T
1
CLK
A
8-15
AD
0-7
ALE
RD
WR
IO/M
STATUS
S
1
S
0
(Fetch)
PC
H
(High Order Address)
PC
L
(Low Order
Address)
(PC+1)
L1
Data from Memory
(Instruction)
T
2
T
3
T
4
T
1
M
2
T
2
T
3
T
1
M
3
T
2
T
3
T
(PC+1)
H
IO Port
Data from Memory
(I/O Port Address)
IO Port
Data to Memory
or Peripheral
10 (Read)
01 Write
11
Figure 5 MSM80C85AH Basic System Timing
10/29
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