FEDD56V72160B-01
OKI Semiconductor
MD56V72160B
*Notes: 1. When CS is set “High” at a clock transition from “Low” to “High”, all inputs except CLK, CKE,
UDQM and LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by BA0 and BA1.
BA0
BA1
Active, read or write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10
0
BA0
0
BA1
0
Operation
After the end of burst, bank A holds the Row-Active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the Row-Active status.
After the end of burst, bank B is precharged automatically.
After the end of burst, bank C holds the Row-Active status.
After the end of burst, bank C is precharged automatically.
After the end of burst, bank D holds the Row-Active status.
After the end of burst, bank D is precharged automatically.
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A12 and A13 inputs.
BA0
0
A10
0
BA1
0
Operation
Bank A is precharged.
0
0
1
Bank B is precharged.
Bank C is precharged.
Bank D is precharged.
All banks are precharged.
1
0
0
1
0
1
X
1
X
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1CLK+ tOHZ ) after UDQM, LDQM entry.
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