FEDL2201-01
Semiconductor
1
ML2201–XXX
AC Characteristics
V
DD
= 2.0 to 5.5 V, GND = 0 V, f
EXTCLK
= 4.096 MHz, Ta = –40 to +85°C (unless otherwise specified)
Parameter
Clock Oscillation Duty Cycle
Reset Input Time after Powering Up
PDWN
Hold Time after Reset Input
D/A Converter Transit Time
(Pop-Noise Canceller Work Time)
Note *1
PDWN
–
ST
Setup Time
ST
–
PI
Setup Time
PI
Pulse Width
PI
Cycle Time
ST
–
PI
Hold Time
ST
– AOUT Setup Time
Note *2
Phrase Stop Time
Note *2
Silence Time between Phrases
Note *2
Stop
ST
Pulse Width
Phrase
ST
– Phrase
ST
Pulse Duration
Note *2
Phrase
ST
– Stop
ST
Pulse Duration
Note *2
Stop
ST
– Phrase
ST
Pulse Duration
Note *2
Sampling Frequency
Note *3
t
PDSS
t
SPS
t
PW
t
PC
t
SPH
t
SAS
t
DPS
t
BLN
t
SSW
t
PP
t
PS
t
SP
f
SAM
—
—
—
—
—
At f
SAM
= 8.0 kHz
At f
SAM
= 8.0 kHz
At f
SAM
= 8.0 kHz
—
At f
SAM
= 8.0 kHz
At f
SAM
= 8.0 kHz
At f
SAM
= 8.0 kHz
—
0.35
1050
1050
500
3.9
1
1
0.35
0.7
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2000
4000
—
1050
700
700
2000
—
—
—
28.0
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
kHz
t
DAR
, t
DAF
—
60
64
68
ms
Symbol
f
DUTY
t
RST
t
PDH
Condition
—
—
—
Min.
40
10
10
Typ.
50
—
—
Max.
60
—
—
Unit
%
µs
µs
Note *1: The value changes in proportion to the external clock frequency, f
EXTCLK
.
Note *2: The value changes in proportion to the sampling frequency, f
SAM
.
Note *3: The sampling frequency is determined by the external clock frequency, f
EXTCLK
, and the dividing
factor that is selected for each phrase.
6/20
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