FEDL66525-02
OKI Semiconductor
ML66525 Family
Classification
Power supply
Symbol
VDD_IO
Type
I
Description
IO Power supply pin
Connect all the VDD _IO pins.*
Core Power supply pin
VDD_CORE
I
Connect all the VDD _CORE pins.*
USB Power supply pin (Vbus input pin)
GND pin
VBUS
GND
I
I
Connect all the GND pins to GND.*
VREF
AGND
XT0
I
I
I
Analog reference voltage pin (Connect to the VDD pin when A/D converter
is not used.)
Analog GND pin (Connect to the GND pin when A/D converter is not
used.)
Oscillation
Sub-clock oscillation input pin
Connect to a crystal of f = 32.768 kHz.
Sub-clock oscillation output pin
Connect to a crystal of f = 32.768 kHz.
The clock output is opposite in phase to XT0.
Main clock oscillation input pin
Connect to a crystal or ceramic oscillator.
When an external clock is used, this pin is configured to be clock input.
Main clock oscillation output pin
Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.
D+ pin
XT1n
OSC0
OSC1n
O
I
O
USB I/F
D+
D–
I/O
I/O
D– pin
PUCTL
RESn
NMI
O
I
I
External control output pin
Reset input pin
Non-maskable interrupt input pin
Test pin
Reset
Others
TEST
I
Connect to the GND pin for normal operation.
Test pin
Connect to the GND pin for normal operation.
Flash ROM programming mode input pin
VTM
I
I
FLAMOD
When the FLAMOD pin is set to “L”, the device enters a programming
mode.
Connect to the VDD_IO pin when using as normal operation.
External program memory access input pin
EAn
I
When the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external program
memory through all address space.
* Connect all VDD_IO pins, all VDD_CORE pins and all GND pins.
If a device has one or more VDD_IO, VDD_CORE, or GND pins to which the power supply or the ground
potential is not connected, the family devices are not guaranteed to have normal operations.
10/27
OKI [ OKI ELECTRONIC COMPONETS ]
