ML675001/ML67Q5002/ML67Q5003
Pin Descriptions (Continued)
Primary/
Pin Name
I/O
Description
Secondary
Logic
RI
O
Ring Indicator.
Secondary
Negative
Indicates that the modem or data set has received a telephone ring indicator. Bit 6 in the
modem status register reflects this input.
SIO Interface
STXD
O
I
SIO transmit signal.
SIO receive signal.
Secondary
Secondary
Positive
Positive
SRXD
I2C Interface
SDA
I/O
O
I2C Data. This pin operates as NMOS Open drain. Connect pull-up resistor.
I2C Clock. This pin operates as NMOS Open drain. Connect pull-up resistor.
Secondary
Secondary
—
—
SCL
Synchronous SIO Interface
SCLK
SDI
I/O
I
Serial clock.
Secondary
Secondary
Secondary
—
—
—
Serial receive data.
Serial transmit data.
SDO
O
Pulse Width Modulator (PWM) Interface
PWMOUT[0]
PWMOUT[1]
O
O
PWM output of Ch 0.
PWM output of Ch 1.
Secondary
Secondary
Positive
Positive
Analog-to-digital Converter Interface
AIN[0]
I
I
Ch 0 analog input
—
—
—
—
—
—
—
—
—
—
—
—
AIN[1]
Ch 1 analog input
AIN[2]
I
Ch 2 analog input
AIN[3]
I
Ch 3 analog input
VREFP
I
Analog-to-digital converter reference voltage
Analog-to-digital converter reference voltage return to ground
VREFN
O
Interrupt Interface
EXINT[3:0]
EFIQ_N
I
I
Interrupt input signals
Secondary
Secondary
Positive / Negative
Negative
Negative-edge-triggered interrupt input signal.Interrupt controller connects this to CPU FIQ
input
MODE Configuration Interface
DRAME_N
I
I
I
I
I
DRAM enable mode
—
—
—
—
—
Negative
Positive
Positive
Positive
—
TEST
Test mode
TEST1
Test mode
FWR
Test mode
JSEL
JTAG select signal: L = On-board debug, H = Boundary scan
Power and Ground Interface
AVDD
Analog-to-digital converter power supply, 3.3 V
Analog-to-digital converter ground
Core power supply, 2.5 V
I/O power supply, 3.3 V
—
—
—
—
—
—
—
—
—
—
AGND
VDD_CORE
VDD_IO
GND
GND for core and I/O
PLLVDD
PLLGND
PLL power supply, 2.5 V
GND for PLL
14 • Oki Semiconductor
April 2004, Rev 2.0
OKI [ OKI ELECTRONIC COMPONETS ]
