FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin Name
External Bus
XA[23:19]
I/O
Description
Primary /
Secondary
Logic
O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM. After a reset, these pins are configured for their primary
function (PIOC[6:2]).
Secondary
Positive
XA[18:0]
XD[15:0]
O
I/O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM.
Data bus to external RAM, external ROM, external I/O banks, and external
DRAM.
—
—
Positive
Positive
External bus control signals (ROM/SRAM/IO)
XROMCS_N
XRAMCS_N
XIOCS_N[0]
XIOCS_N[1]
XIOCS_N[2]
XIOCS_N[3]
XOE_N
XWE_N
XBS_N[1:0]
XBWE_N[0]
XBWE_N[1]
XWR
O
O
O
O
O
O
O
O
O
O
O
O
ROM bank chip select
SRAM bank chip select
IO chip select 0
IO chip select 1
IO chip select 2
IO chip select 3
Output enable/ Read enable
Write enable
Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB
LSB Write enable
MSB Write enable
Data transfer direction for external bus, used when connecting to Motorola
I/O devices. This represent the secondary function of pin PIOC[7].
L: read , H: write.
XWAIT
I
Available for I/O bank 0/1.
Secondary
Positive
External I/O bank 0/1/2/3 WAIT signal.
This input permits access to devices slower than register settings.
—
—
—
—
—
—
—
—
—
—
—
Secondary
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
—
External bus control signals (DRAM)
XRAS_N
XCAS_N
XSDCLK
XSDCKE
XSDCS_N
XDQM[1]/XCAS_N[1]
XDQM[0]/XCAS_N[0]
O
O
O
O
O
O
O
Row address strobe. Used for both EDO DRAM and SDRAM
Column address strobe signal (SDRAM)
SDRAM clock (same frequency as internal HCLK)
Clock enable (SDRAM)
Chip select (SDRAM)
Connected to SDRAM: DQM (MSB)
Connected to EDO DRAM: column address strobe signal (MSB)
Connected to SDRAM: DQM (LSB)
Connected to EDO DRAM: column address strobe signal (LSB)
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Negative
Negative
—
—
Negative
Positive/
Negative
Positive/
Negative
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