FEDL7020-02
1
Semiconductor
ML7020
PIN DESCRIPTIONS
Pin No.
1
2
Symbol
V
DD
TIO
O
I/O
Power supply pin.
Description
Connect a +5 V power supply to this pin.
The output pin of the input amplifier 1. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and TI– (3) so as to attenuate
high frequency components above 10 kHz.
The inverting input pin for the input amplifier 1. When the input amplifier 1 is not
used, connect pin TIO (2) to pin TI– (3), and connect pin TI+ (4) to pin SGO.
The non-inverting input pin for the input amplifier 1.
The output pin for the input amplifier 2. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI1– (6) so as to attenuate
high frequency components above 10 kHz.
The inverting input pin for the input amplifier 2. When the input amplifier 2 is not
used, connect pin LI1O (5) and LI1– (6), and connect pin LI+ (7) to pin SGO.
The non-inverting input pin for the input amplifier 2.
The input pin for SW3.
to be made ON.
This pin is connected internally to SGO (9) when SW3 is
A voltage of about V
DD
/2 is
3
4
5
TI–
TI+
LI1O
I
I
O
6
7
8
9
LI1–
LI1+
SWI
SGO
I
I
I
O
The signal ground output pin for external circuits.
output from this pin.
10
LI2O
O
The output pin for the input amplifier 3. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI2– (10) so as to attenuate
high frequency components above 10 kHz.
The inverting input pin for the input amplifier 3.
When the input amplifier 3 is not used, connect pin LI2O (10) and LI2– (11).
The output pin of the output amplifier 1.
Can drive a load of 1.2 kΩ or more.
The non-inverting output pin for the output amplifier 2. See Figure 2 for details
of connecting a peripheral circuit.
The inverting output pin of the output amplifier 2.
connecting a peripheral circuit.
The signal ground output pin for internal circuits.
output from this pin.
The ground pin for the LSI.
See Figure 2 for details of
A voltage of about V
DD
/2 is
11
12
13
14
LI2–
TO
LO+
LO–
I
O
O
O
15
16
17
SGC
GND
CSB
O
Connect a 1
µF
capacitor between SGC (15) and GND (16).
Connect a 0 V input to this pin.
Reading and writing are
The chip select pin for the processor interface.
I
Reading and writing are possible when this input is “0”.
disabled when this input is “1”.
The read control pin for the processor interface.
Data can be read from the LSI when this pin is “0”.
The write control pin for the processor interface.
Data is written into this LSI at the rising edge of the WR signal.
The address input pin A0 for the processor interface.
18
19
20
RDB
WRB
A0
I
I
I
4/19
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