1Semiconductor
ML7021
AC Characteristics
Parameter
(Ta = –40˚C to +85˚C)
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
Symbol
Unit
Min.
Typ.
19.2
—
Max.
Min.
Typ.
19.2
—
Max.
Clock Frequency
—
17.5
—
—
20
—
17.5
—
—
20
fC
MHz
When Internal Sync Signal is not used
Clock Cycle Time
52.08
—
—
52.08
—
—
tMCK
tDMC
tMCH
ns
ns
ns
When Internal Sync Signal is not used
Clock Duty Ratio
50
57.14
60
50
57.14
60
40
—
40
—
Clock High Level Pulse Width
fc = 19.2 MHz
20.8
20.8
—
—
31.3
31.3
20.8
20.8
—
—
31.3
31.3
Clock Low Level Pulse Width
fc = 19.2 MHz
tMCL
ns
Clock Rise Time
tr
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
—
—
5
5
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
—
—
5
5
ns
ns
ns
kHz
ms
%
Clock Fall Time
tf
Sync Clock Output Time
Internal Sync Clock Frequency
Internal Sync Clock Output Cycle Time
Internal Sync Clock Duty Ratio
Internal Sync Signal Output Delay Time
Internal Sync Signal Period
tDCM
fCO
—
30
—
—
—
5
—
30
—
—
—
5
256
3.9
50
256
3.9
50
tCO
tDCO
tDCC
tCYO
—
—
ns
ms
ms
kHz
ms
%
125
tCO
—
—
—
2048
15.6
60
—
—
125
tCO
—
—
—
2048
15.6
60
—
—
Internal Sync Signal Output Width tWSO
Transmit/receive Operation Clock Frequency
Transmit/receive Sync Clock Cycle Time
Transmit/receive Sync Clock Duty Ratio
Transmit/receive Sync Signal Period
fSCK
tSCK
tDSC
tCYC
tXS
—
—
50
50
125
—
125
—
ms
ns
ns
ms
ns
ns
ms
ns
ms
ns
ns
ms
ns
ns
ms
Sync Timing
tSX
—
—
tCYC-tSCK
—
tCYC-tSCK
—
Sync Signal Width
tWSY
tDS
—
—
Receive Signal Setup Time
Receive Signal Hold Time
Receive Data Input Time
IRLD Signal Output Delay Time
IRLD Signal Output Width
—
—
tDH
—
—
—
—
tID
7tSCK
—
—
7tSCK
—
—
tDIC
tWIR
tSD
138
—
138
—
tSCK
—
tSCK
—
90
90
Serial Output Delay Time
tXD
—
90
—
90
Reset Signal Input Width
Reset Start Time
tWR
tDRS
tDRE
tDIT
—
—
—
—
5
—
—
5
—
—
Reset End Time
—
100
—
52
—
100
—
52
Processing Operation Start Time
—
—
—
—
10
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