FEDL70511LA-03
1
Semiconductor
TEST I/F
Pin Name
TEST_L
TEST_H
TEST_PU
VTM
NC
Direction
I
I
Oc
I
—
Internal
Pull Up/Down
—
—
—
—
—
Initial
Value
—
—
L
—
—
Pin
Placement
[*4]
D4
B5
C9
A1, A13,
N1, N13
Test pin (input)
Test pin (input)
Test monitor pin
Test pin
No Connection
Description
ML70511LA
Power, GND
Pin Name
V
DD
LVDD
GND
AVDD0
AVDD1
AGND0
AGND1
REGVDD
REGGND
REGOUT
REGVBG
Direction
—
—
—
—
—
—
—
—
—
—
—
Internal
Pull Up/Down
—
—
—
—
—
—
—
—
—
—
—
Initial
Value
—
—
—
—
—
—
—
—
—
—
—
Pin
Placement
[*5]
E4
[*6]
E13
C11
E11
A11
E12
F13
F12
E10
Description
I/O power pin 3.3 V ±0.3 V
I/O power pin 3.3 V ±0.3 V (Same voltage
to the V
DD
for ML7050LA)
Digital block ground pin
Analog block power pin 2.5 V ±0.25 V
(Connect to REGOUT pin: F12)
Analog block ground pin
(Connect to REGGND pin: F13)
Regulator power pin (3.0 to 3.6 V)
Regulator ground pin
Regulator output
Regulator reference voltage tuning
[*4]
[*5]
[*6]
TEST_L (TEST5): A8
TEST_L (TEST4): D8
TEST_L (TEST3): C8
TEST_L (TEST2): B7
TEST_L (TEST1): D7
TEST_L (TEST0): B6
TEST_L (PLLSEL): C10
TSET_L (PLLEN): A12
TSET_L (SVCO1): B3
C6, G1, K7, J12, H11, D12, L10
B11, C7, A6, A4, E2, F3, J2, N5, L6, M8, N12, H13, G12, F10, C12
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