FEDL87V5002-01
OKI Semiconductor
ML87V5002
I
2
C Interface Timing
The internal register setting is done via I
2
C Interface. The interface is based on the standard mode I
2
C bus (SCL
frequency = 100 kHz).
Fig. 6 shows the basic timing. Table 1 summarizes the AC Characteristics of the standard mode I
2
C bus. Do not
change the “SDA” level as long as the “SCL” is high except the stop or start condition. Refer to the “AC
Characteristics” to know the values of timing parameters.
SDA
MSB
SCL
S
Start Condition
1
2
7
8
9
ACK
1
2
9
P
Stop Condition
t
DSI2C
t
DHI2C
t
CCI2C
t
HI2C
t
LI2C
2
Figure 6 I C Interface Basic Timing
Table 1 AC Characteristics of Standard Mode I
2
C Bus (SCL Frequency = 100 kHz)
Parameter
Reset Pulse Time
I C Clock Cycle Time
I
2
C Clock High-Level Time
I
2
C Clock Low-Level Time
I
2
C Data Setup Time
I C Data Holdup Time
2
2
Symbol
t
RSTP
t
CCI2C
t
HI2C
t
LI2C
t
DSI2C
t
DHI2C
Min.
100
10
4
4.7
250
0
Max.
3.45
Unit
ns
µs
µs
µs
ns
µs
Power-On
For the normal operation of the ML87V5002, the pins other than the RESET pin should be maintained at a low
level until the VCC has reached the specified voltage level after powered on. Thereafter this LSI is reset by
maintaining the RESET pin at a low level for 1 ms or more. The release of the RESET level leads to starting
normal operation.
To reset this LSI during normal operation, set the RESET pin at a “L” level for a time t
RSTP
or more.
To power on again after powered off, verify that VCC is 0 V.
Power-on
VCC min
VCC
0V
1 ms (min.)
t
RSTP
VCC
0V
RESET
Figure 7 Power-On Sequence
8/36
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