PEDL9041-03
1
Semiconductor
ML9041-xxA/xxB
(GND = 0 V, VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)
Applicable
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
pins
VDD = 5 V, 1/5 bias
Maximum and
minimum LCD
drive voltages
when internal
variable resistors
are used.
VLCD
MAX
V5IN = 0 V,
4.6
—
V
VDD–V5
Contrast data: 1F
VDD = 5 V, 1/5 bias
VLCD
MIN
V5IN = 0 V,
—
3.4
V
V
Contrast data: 00
Bias Voltage for
Driving LCD by
External Input
VLCD1
VLCD2
1/5 bias
2.8
2.8
—
—
7.0
7.0
V5
VDD–V5
Note 7
1/4 bias
VDD = 3 V, VIN = 0 V
f = 270 kHz
Voltage Multiplier
Output Voltage
A capacitor for the voltage VDD–(VDD–VIN)
VDD–(VDD–
×
VIN) 2+1.2 V
V5OUT
—
V
V
V5, V5IN
µ
×
multiplier = 4.7 F
2–0.1
No load
BEB = H
Voltage Multiplier
Input Voltage
VIN
VDD–3.5 V
VDD/2
VIN
Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the
µ
common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one common
pin.
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and
µ
any of the segment pins (SEG1 to SEG100) when the current of 4 A flows in or flows out at one
common pin.
µ
The current of 4 A flows out when the output level is VDD or flows in when the output level is
V5.
Note 2: Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is
fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = 5 V
GND = V5 = 0 V,
V1, V2, V3A (V3B) and V4: Open
E, SSR, CSR, and BEB: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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