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• Data write
WR
ML9052
MPU
DATA
N
Latch
N
N+1
N+1
N+2
N+2
N+3
N+3
Internal timing
BUS Holder
Write Signal
Figure 2(a)
• Data read
WR
MPU
RD
DATA
Address
Preset
N
N
n
n+1
Internal timing
Read Signal
Column
Address
BUS Holder
Preset N
N
Increment N+1
n
n+1
N+2
n+2
Address Set
#n
Dummy
Read
Data Read
#n
Data Read
#n+1
Figure 2(b)
• Busy flag
The busy flag being "1" indicates that the ML9052 is carrying out internal operations, and hence
no instruction other than a status read instruction is accepted during this period. The busy flag
is output at pin D7 when a status read instruction is executed. If the cycle time (t
CYC
) is
established, there is no need to check this flag before issuing every command and hence the
processing performance of the MPU can be increased greatly.
11/64
OKI [ OKI ELECTRONIC COMPONETS ]
