FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
BLOCK DIAGRAM
ML9092-01
COM1
V
IN
V
S1–
V
C1+
V
OUT
COM10 PB0
PB2 SEG1
SEG56
Voltage
Doubler
10 Output
Common
Drivers
3 Port
Drivers
56 Output
Segment Drivers
Shift
Register
Data Latch
V
0
Line Address Decoder
V
2
Display Data RAM
56
×
10 Bit
CP
DI/O
Control
Register
CS
Input Output
Interface
I/O
Buffer
X Address Decoder
X Address Counter
Timing
Generator
X Address Register
OSC1
OSC2
Oscillation
Circuit
1 Port Driver
RESET
TEST
V
DD
V
SS
PA0
KPS
C0/ C1/
D0 D1
5
×
5 Key Scan/10 Port Drivers
and Encoder Switch Interface
C2/ C3/
D2 D3
C4/ R0/ R1/ R2/ R3/ R4/ A
D4 C0 C1 C2 C3 C4
B KREQ
3/66
Display Line Counter
Y Address Decoder
Y Address Register
Y Address Counter
LCD Bias
Voltage
Driving
Circuit
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