FEDL9090A-01
1
Semiconductor
ML9090A-01, -02
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
Function
Pin
85
CPU interface
84
86
87
100
Oscillation
101
OSC2
O
Symbol
CS
CP
DI/O
KREQ
OSC1
Type
I
I
I/O
O
I
Description
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to an internal Schmitt circuit
Serial data signal I/O pin
Key request signal output pin
Connect external resistors.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Initial settings can be established by
pulling the reset input to a “L” level. This
pin is connected to an internal Schmitt
circuit.
Input pin for selecting the voltage doubler
or voltage tripler.
Test input pin. This pin is connected to the
V
SS
pin.
Input pins that detect status of key
switches
Key switch scan signal output pins
Port A output
Port B outputs (for ML9090A-01)
Outputs for LCD segment drivers
Outputs for LCD common drivers
(for ML9090A-01)
Outputs for LCD common drivers
(for ML9090A-02)
Logic power supply pin
GND pin
Voltage multiplier reference voltage power
supply pin
Capacitor connection pins for voltage
multiplier
Voltage multiplier output pin
Voltage multiplier output pin
LCD bias pins
88
Control signals
99
89
83 to 79
78 to 74
Port outputs
103
111 to 104
73 to 122
LCD driver outputs
121 to 112
121 to 104
102
90
95
Power supply
94, 93
92
91
98, 96, 97
RESET
I
DT
TEST
C0
to
C4
R0
to
R4
PA0
PB0 to PB7
SEG1 to
SEG80
COM1 to
COM10
COM1 to
COM18
V
DD
V
SS
V
IN
V
C1
, V
C2
V
S1
V
S2
V
2
, V
3A
, V
3B
I
I
I
O
O
O
O
O
O
—
—
—
—
—
—
—
Key scan signals
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