FEDR27V802F-01-03
OKI Semiconductor
MR27V802F / OTP
BLOCK DIAGRAM
A–1
× 8/× 16 Switch
CE#
CE
OE#
OE
BYTE#/V
PP
PGM
Column Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Row Decoder
Memory Cell Matrix
524,288 × 16-Bit or 1,048,576× 8-Bit
Address Buffer
Multiplexer
Output Buffer
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D12
D14
D15
D11
D13
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
Output disable
Standby
Program
Program inhibit
Program verify
CE#
L
L
L
H
L
H
H
OE#
L
L
H
∗
H
H
L
BYTE#/V
PP
H
L
H
L
H
L
8.0 V
V
CC
D0 to D7
D
OUT
3.3 V
D8 to D14
D
OUT
Hi–Z
Hi–Z
Hi–Z
D
IN
Hi–Z
D
OUT
Hi-Z
Hi-Z
Hi-Z
D15/A–1
L/H
∗
∗
L/H
L/H
L/H
4.0 V
∗:
Don’t Care (H or L)
3/15