PEDD514400EL-01
MSM514400E/EL
Notes:
1.
A start-up delay of 200µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or
CAS
before
RAS
refresh) before proper device
operation is achieved.
The AC characteristics assume t
T
= 5ns.
V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition
times (t
T
) are measured between V
IH
and V
IL
.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, then the access time is controlled by t
AA
.
t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
t
RCH
or t
RRH
must be satisfied for a read cycle.
t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire
cycle. If t
CWD
≥
t
CWD
(Min.), t
RWD
≥
t
RWD
(Min.), t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.),
then the cycle is a read modify write cycle and data out will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at
access time) is indeterminate.
2.
3.
4.
5.
6.
7.
8.
9.
10. These parameters are referenced to the
CAS,
leading edges in an early write cycle, and to the
WE
leading edge in an
OE
control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and
CAS
before
RAS
refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a
RAS-only
refresh cycle or a
CAS
before
RAS
refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
8/14
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