FEDD51V17405F-01
1
Semiconductor
MSM51V17405F
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC
.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
t
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ, and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD
(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test CA9 and CA10 are not used and
each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written
in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a
high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared
and the memory device returned to its normal operating state by performing a RAS-only refresh cycle
or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
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