FEDS51V4222C-03
Semiconductor
1
MSM51V4222C
BLOCK DIAGRAM
D
OUT
(× 4)
Data-Out
Buffer (× 4)
RE
RSTR
SRCK
Serial Read Controller
512-Word Serial Read Register (× 4)
Read Line Buffer Read Line Buffer
Low-Half (
×
4)
High-Half (
×
4)
256 (× 4)
120-Word
Sub-Register (× 4)
256 (× 4)
120-Word
Sub-Register (× 4)
256K (× 4)
Memory
Array
X
Decoder
Read/Write
and Refresh
Controller
256 (× 4)
256 (× 4)
Clock
Oscillator
Write Line Buffer Write Line Buffer
Low-Half (
×
4)
High-Half (
×
4)
512-Word Serial Write Register (× 4)
Data-In
Buffer (× 4)
V
BB
Generator
Serial Write Controller
D
IN
(× 4)
WE
RSTW
SWCK
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