E2L0016-17-Y1
¡ Semiconductor
MSM548262
¡ Semiconductor
262,144-Word
¥
8-Bit Multiport DRAM
This version: Jan. 1998
MSM548262
Previous version: Dec. 1996
DESCRIPTION
The MSM548262 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit
dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and
asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548262
features block write, flash write functions on the RAM port and a split data transfer capability
on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-
flops.
FEATURES
•
RAS
only refresh
• Single power supply: 5 V
±10%
•
CAS
before
RAS
refresh
• Full TTL compatibility
• Hidden refresh
• Multiport organization
• Serial read/write
RAM : 256K word
¥
8 bits
• 512 tap location
SAM : 512 word
¥
8 bits
• Bidirectional data transfer
• Fast page mode
• Split transfer
• Write per bit
• Masked write transfer
• Masked flash write
• Refresh: 512 cycles/8 ms
• Masked block write
• Package options:
40-pin 400 mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM548262-xxJS)
44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548262-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM548262-60
MSM548262-70
MSM548262-80
Access Time
RAM
60 ns
70 ns
80 ns
SAM
17 ns
17 ns
20 ns
Cycle Time
RAM
120 ns
140 ns
150 ns
SAM
22 ns
22 ns
25 ns
Power Dissipation
Operating
140 mA
130 mA
120 mA
Standby
8 mA
8 mA
8 mA
1/37
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