PEDL66577-01
1Semiconductor
MSM66577 Family
(2) Multiplexed bus type
External program memory control
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Parameter
Cycle time
Symbol
Condition
Min.
33.3
Max.
—
Unit
tcyc
tφWH
tφWL
TAW
tPW
fOSC = 30 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
13
—
13
—
2 tφ – 10
2 tφ – 15
tφ – 3
2tφ – 15
tφ – 3
3tφ – 25
0
—
PSEN pulse width
—
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
tPAD
tALS
tALH
tAHS
tAHH
tIS
—
ns
CL = 50 pF
—
—
—
—
25
—
tIH
0
tφ – 3
Note: tφ = tcyc/2
tcyc
CPUCLK
tφWH
tφWL
tAW
ALE
PSEN
tPAD
tPW
AD0 to AD7
A8 to A19
PC0 to 7
INST0 to 7
tIS
tIH
tALS
tALH
PC8 to 19
tAHH
tAHS
Bus timing during no wait cycle time
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