PEDL66577-01
Semiconductor
1
MSM66577 Family
BLOCK DIAGRAM
TM0OUT
TM0EVT
TM1OUT
TM1EVT
TM2OUT
TM2EVT
CLKOUT
XTOUT
RXD1
TXD1
RXC1
TXC1
TM4OUT
RXD6
TXD6
RXC6
TXC6
16 bit Timer0
CPU Core
8 bit Timer1
8 bit Timer2
System
Control
Peripheral
SIO1
(UART/SYNC)
ALU Control
ACC
ALU
Control
Registers
SSP
LRB
PSW
PC
CSR
XT0
XT1
OSC0
OSC1
HOLD
HLDACK
RES
8 bit Time4/BRG
SIO6
(UART/SYNC)
Memory Control
Pointing Registers
Local Registers
DSR TSR
8 bit Timer3/BRG
SIOI4
SIOO4
SIOCK4
SIO4
(32 byte FIFO SYNC)
Instruction
Decoder
EA
SELMBUS
PSEN
RD
WR
WAIT
D0 to D7
(AD0 to AD7*)
A0 to A19
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P14
P15
8 bit Timer5/BRG
SIOI5
SIOO5
SIOCK5
SIO5
(32 byte FIFO SYNC)
RAM
4K
ROM
128K
Bus Port Control
8 bit Timer6/WDT
PWMOUT0
PWMOUT2
PWMOUT1
PWMOUT3
8 bit Timer9
CPCM0
CPCM1
CAP/CMP
16 bit FRC
V
REF
AGND
AI0
to
AI7
AO0
AO1
NMI
EXINT0
to
EXINT7
10 bit A/D
Converter
8 bit D/A Converter
8 bit PWM0
8 bit PWM1
TBC
RTC
Interrupt
*: Address output/data I/O when
selecting multiplexed bus type.
Port Control
5/34
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