¡ Semiconductor
MSM7540L/7560L
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
BCLKB
XSYNC
PCMSO
PCMSO
(during linear)
0
txs
tsx
1
2
tws
txd2
3
4
5
6
7
8
9
10
11
12
13
14
txd1
txd3
MSB
tsdx
LSB
txd3
MSB
LSB
BCLKA
XSYNC
IS
0
txs
tsx
txd1
tsdx
1
2
txd2
3
4
5
txd3
6
7
8
9
10
MSB
LSB
Receive Side PCM/ADPCM Data Interface
BCLKA
RSYNC
tds
tdh
txd3
0
trs
tsr
1
2
tws
3
4
5
6
7
8
9
10
11
12
13
14
IR
0
trs
MSB
LSB
BCLKB
RSYNC
tsr
1
2
3
4
5
6
7
8
9
10
trd1
trd2
txd3
PCMRO
tsdx
MSB
MSB
LSB
trd3
PCMRO
(during linear)
LSB
Note: Linear format
A code of an input/output level is determined by the 14-bit 2'compliment.
Refer to the table below for code format.
Input/Output level
+Full-scall
0
–Full-scall
MSB to LSB
01111111111111
00000000000000
10000000000000
12/15
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