¡ Semiconductor
MSM7704-01/02/03
TIMING DIAGRAM
Transmit Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
XSYNC
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
DOUT1
DOUT2
D2
D4
D5
D6
D7
Transmit Side
Receive Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tRS
tSR
tWS
RSYNC
tDS
tDH
DIN1
DIN2
MSD
D2
D3
D4
D5
D6
D7
D8
Receive Side
Figure 1 Timing Diagram in the Parallel Mode (CHPS = 1)
BCLK
XSYNC
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
DOUT1
CH1 PCM Data
CH2 PCM Data
Transmit Side
BCLK
RSYNC
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
DIN2
CH1 PCM Data
CH2 PCM Data
Receive Side
Figure 2 Timing Diagram in the Serial Mode (CHPS = 0)
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