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SYNC
MSM7716
Synchronizing signal input.
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously
with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN
pin by the synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK.
When this signal frequency is 8 kHz, the transmit and receive section have the frequency
characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in
this data sheet.
For different frequencies of the SYNC signal, the frequency values in this data sheet should be
translated according to the following equation:
Frequency values described in the data sheet
¥
the SYNC frequency values to be actually used
8 kHz
Setting this signal to logic "1" or "0" drives the device to power-saving state.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal synchronously with the
SYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the
internal register when shifted by 14 bits.
The top of the data (MSD) is identified at the rising edge of SYNC.
The input signal should be input in the 14-bit 2's complement format.
The MSD bit represents the polarity of the signal with respect to the signal ground.
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