¡ Semiconductor
DMA (Master) Mode (continued)
Symbol
t
DCL
t
DCTR
t
DCTW
t
DQ
t
EPS
t
EPW
t
FAAB
t
FAC
t
FADB
t
HS
t
IDH
t
IDS
t
ODH
t
ODV
t
QS
t
RH
t
RS
t
STL
t
STT
Item
Delay Time from CLK Rising Edge
to Read/Write Signal Leading Edge
Delay Time from CLK Rising Edge
to Read Signal Trailing Edge
Delay Time from CLK Rising Edge
to Write Signal Trailing Edge
Delay Time from CLK Rising Edge
to HRQ Valid
EOP
Leading Edge Set-up Time to
CLK Falling Edge
EOP
Pulse Width
Delay Time from CLK Rising Edge
to Address Valid
Time from CLK Rising Edge
up to Active Read/Write Signal
Delay Time from CLK Rising Edge
to Data Valid
HLDA Valid Set-up Time
to CLK Rising Edge
Input Data Hold Time
to
MEMR
Trailing Edge
Input Data Set-up
to
MEMR
Trailing Edge
Output Data Hold Time
to
MEMW
Trailing Edge
Time from Output Data Valid
to
MEMW
Trailing Edge
DREQ Set-up Time
to CLK Falling Edge
READY Hold Time
to CLK Falling Edge
READY Set-up Time
to CLK Falling Edge
Delay Time from CLK Rising Edge
to ADSTB Leading Edge
Delay Time from CLK Rising Edge
to ADSTB Trailing Edge
Min.
—
—
—
—
40
220
—
—
—
75
0
170
10
125
0
20
60
—
—
Max.
190
190
130
120
—
—
170
150
200
—
—
—
—
—
—
—
—
130
90
MSM82C37B-5RS/GS/VJS
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
(Note 2)
(Note 2)
(Note 2)
—
—
—
—
—
—
—
—
—
—
—
(Note 3)
—
—
—
—
6/33
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