74HC74
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
su
Parameter
Minimum Setup Time, Data to Clock
(Figure 3)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
– 55 to
25_C
80
35
16
14
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
60
25
12
10
60
25
12
10
1000
800
500
400
v
85_C
100
45
20
17
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
75
30
15
13
75
30
15
13
1000
800
500
400
v
125_C
120
55
24
20
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
90
40
18
15
90
40
18
15
1000
800
500
400
Unit
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
ns
t
rec
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
ns
t
w
Minimum Pulse Width, Set or Reset
(Figure 2)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figures 1, 2, 3)
ns
ORDERING INFORMATION
Device
74HC74D
74HC74DG
74HC74DR2
74HC74DR2G
74HC74DTR2
74HC74DTR2G
Package
SOIC−14
SOIC−14
(Pb−Free)
SOIC−14
SOIC−14
(Pb−Free)
TSSOP−14*
TSSOP−14*
2500 / Tape & Reel
55 Units / Rail
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
4
ONSEMI [ ON SEMICONDUCTOR ]
